1. Field of the Invention
The present invention relates generally to semiconductor devices and, more specifically, the present invention relates to a high voltage field effect transistor with an improved gate design.
2. Background Information
A common type of integrated circuit device is a metal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET is a field effect device that includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate provided over the channel region. The gate includes a conductive gate structure disposed over and separated from the channel region with a thin oxide layer.
For high voltage applications, such as for example applications greater than 200 volts, lateral power transistors are often used. A cross-section from one such device 101 is shown in FIG. 1A. Device 101 is a field effect device including a drain region 120 and a source region 124 separated by an intermediate region 107. A gate structure 113 is disposed over a thin oxide layer 128 over the metal-oxide-semiconductor (MOS) channel 132 of device 101. In device 101, the MOS channel 132 under gate structure 113 is included in intermediate region 107.
In the on state, a voltage is applied to a gate structure 113 to cause the MOS channel 132 to form between an N+ source region 124 and an N well region 108, allowing current to flow from N+ drain region 120, through N well 108, through the MOS channel 132, into the N+ source region 124. In the off state, the voltage on gate structure 113 is reduced such that the MOS channel 132 is removed, thereby interrupting the current flow path. In this condition, high voltage is supported between drain region 120 and source region 124 via mutual depletion of N well 108 and substrate 106. In the device 101 shown in FIG. 1A, a P-region 130 is also included along the surface of N well 108 to assist depletion of N well 108.
To help prevent or control high electric fields from developing at either end of device 101, which would degrade the breakdown voltage, it is common to form field plates over the source and drain regions. In device 101, a drain field plate is formed with a drain electrode finger 119 extending over interlevel dielectric 122 to form a one-tiered drain field plate. A three-tiered source field plate is formed by gate structure 113 over thin gate oxide 128, gate structure 113 over field oxide 126 and source electrode finger 125 over interlevel dielectric 122. Therefore, gate structure 113 serves two roles: controlling the flow of current (switching device 101 on and off) and acting as a portion of the source field plate.
Lateral power transistors are commonly designed in an interdigitated arrangement. To illustrate, FIG. 1B is a layout diagram of prior art device 101, which has interdigitated source and drain regions. The cross section illustration of FIG. 1A corresponds to dashed line 140 illustrated in FIG. 1B. Device 101 includes a drain electrode 105, source electrode 103 and gate electrode 109. Drain electrode 105 includes drain electrode fingers 117, 119 and 121. Source electrode 103 includes source electrode fingers 123 and 125. Drain electrode 105 is coupled to a doped drain region below (shown as drain region 120 in FIG. 1A) in the semiconductor substrate and source electrode 103 is coupled to a doped source region below (shown as source region 124 in FIG. 1A) in the semiconductor substrate. Intermediate region 107 extends between the drain and source regions of drain and source electrodes 105 and 103, respectively. Intermediate region 107 includes the channel region or MOS channel region 132 and extends beneath gate structures 111, 113 and 115.
As shown in FIG. 1B, the layout of device 101 includes alternating fingers of the drain and source electrodes 105 and 103. To increase device efficiency and reduce the inactive area associated with the ends of the fingers of drain and source electrodes 105 and 103, the fingers are generally made as long as possible, within the confines of the desired size of the integrated circuit. To achieve this end, the length L is generally increased.
Gate electrode 109 is coupled to gate structures 111, 113 and 115 through metal contacts 127, 129, 131, 133, 135 and 137. As shown in FIG. 1B, gate structures 111, 113 and 115 are disposed beneath source electrode 103 and are also disposed over a portion of intermediate region 107. A thin gate oxide layer exists under gate structures 111, 113 and 115. Gate structures 111, 113 and 115 control the flow of current between the source and drain regions. In MOS lateral power transistors such as device 101, gate structures 111, 113 and 115 are disposed in close proximity to source electrode 103 including fingers 123 and 125.
In order to provide high breakdown voltage, it is desirable to maintain the relative positions of the gate structure, the source electrode, the intermediate region and the drain electrode. In particular, the gate structure and the electrodes should not protrude into the intermediate region at any point along the length of the device. Moreover, it is desirable to maintain rounded geometries at the end of the fingertips in order to help prevent or control high electric fields in these areas. These features of high voltage devices preclude the use of techniques sometimes used in low voltage complementary metal oxide semiconductor (CMOS) devices, such as the extension of the gate structure on either end of the fingertips to allow contact to a gate electrode.
Gate structures 111, 113 and 115 are usually made of polysilicon layers having sheet resistances of about 20-60 ohms/square. The thin gate oxide layers under the gate structures and above the channel region 132 of intermediate region 107 are usually relatively thin (e.g. &lt;1000 Angstroms) and cover some portion of the underlying source and drain doped regions. Since fingers 117, 119, 121, 123 and 125 can be relatively long (e.g. 2-8 mm) the total gate resistance as well as the gate-source and gate-drain capacitance can be significant. When the gate of device 101 is switched on and off, this large capacitance must be charged and discharged through the gate resistance, leading to a resistor-capacitor (RC) delay in the switching characteristics of device 101.
As shown in FIG. 1B, gate electrode 109 is located on one end of device 101. Gate structures 111, 113 and 115 distribute a gate signal received from gate electrode 109 along the length of each finger. For example, gate structure 111 distributes the gate signal along the length of source finger 123. Gate structure 113 distributes the gate signal along the length of source finger 125. Gate structure 115 distributes the gate signal along the lengths of other fingers along the sides of source electrode 103.
The presence of the above mentioned RC delay can be beneficial as the delay can slow the voltage transients in the device and therefore reduce switching noise. The switching noise includes harmonics associated with very fast changes in voltage and/or current. In addition, since gate electrode 109 does not run along the length of the source fingers, the source electrode 103 can be wider and this can conduct more current.
To illustrate, FIG. 2 is an enlarged view of region 139 of device 101 of FIG. 1. Source electrode 103 includes source electrode finger 125. Intermediate region 107 extends between the source and drain regions of source electrode finger 125 and drain electrode fingers 119 and 121. Intermediate region 107 includes a channel region that extends beneath gate structure 113. Gate structure 113 is disposed beneath source finger 125 and is coupled to gate electrode 109 through contacts 133 and 135. As shown in FIG. 2, gate electrode 109 is located at an end of device 101. Since gate electrode 109 does not run along the sides of source electrode finger 125, the width W of source electrode finger 125 can be wider and conduct more current.
A disadvantage of device 101 as illustrated in FIGS. 1-2 is that the turn-on and turn-off of device 101 can be non-uniform along the lengths of the fingers. In particular, the portion of device 101 that is at the end of a finger closest to the contact of gate electrode 109 turns off more quickly than the end of the finger that is farthest from the contact. Because the drain voltage rises relatively quickly during the turn-off, the end of the finger figure that is farthest from the contact is exposed to high voltage and high current simultaneously. This non-uniform switching results in a degradation of the safe-operating area (SOA) of device 101 and consequently limits the length L of the fingers.
To illustrate the SOA of device 101, FIG. 4 is a diagram of the percentage of devices that fail when subjected to a given peak drain current I.sub.D in a given inductive switching application such as for example an AC-DC power converter circuit. Plot 403 shows that the percentage of failures for device 101 with a shorter length L and plot 405 shows the percentage of failures for device 101 with a longer length L. Plot 403 shows that the maximum current I.sub.MAX1, which is defined as the peak drain current I.sub.D causing 50% failure rate, for device 101 having the shorter length L is greater than the maximum current I.sub.MAX2 for device 101 having a longer length. Hence, if the length of device 101 is increased, the maximum drain current I.sub.D (and SOA) is sacrificed as a consequence of the non-uniform switching discussed above.
FIG. 3 is an illustration of a prior art device 301 that addresses the above-discussed problem of non-uniform switching. Device 301 reduces the RC delay discussed above to provide more uniform switching. In particular, FIG. 3 shows that gate electrode 309 is located at the end of device 301, and a second gate electrode 310 is also run in parallel along the sides of source electrode finger 325 of source electrode 303 to supply the gate signal to the gate structure 313 along the length of the finger. Intermediate region 307 separates the source and drain regions of source electrode 303 from drain electrode fingers 319 and 321. Intermediate region 307 includes a channel that extends beneath gate structure 313. Gate structure 313 is disposed beneath gate electrodes 309 and 310 and source electrode 303. Gate electrode 309 is coupled to gate structure 313 through contacts 333 and 335. Gate electrode 310 is coupled to gate structure 313 through contacts 341 and 343.
As shown in FIG. 3, contacts 341 and 343 are continuous along the sides of source electrode finger 325 and therefore make continuous contact between gate electrode 310 and gate structure 313 for the length of source electrode finger 325. As a result, the gate resistance of device 301 is much less than the gate resistance of device 101 since gate electrode 310 generally has a much lower sheet resistance than gate structure 313. For example, gate electrode 310 is usually made of metal having a sheet resistance of less than approximately 0.05 ohms/square. In comparison, gate structure 313 is usually made of polysilicon having a sheet resistance of approximately 20-60 ohms/square. With the lowered gate resistance, the RC delay discussed above is reduced accordingly. This results in device 301 switching on and off uniformly, which makes the SOA of device 301 independent of finger length.
A disadvantage with device 301 is that the reduction in the RC delay may be too great such that excessive switching noise may be produced by rapid voltage transients. Another disadvantage with the addition of continuous contacts 341 and 343 is that with gate electrode 310 running in parallel along the sides of source electrode finger 325, the width W of source finger 325 is reduced in comparison with device 101 of FIGS. 1-2. The maximum amount of current that source electrode finger 325 can handle is limited by electromigration and other concerns, and is approximately proportional to W. Consequently, the maximum amount of current that device 301 can handle is lower than device 101.
Thus, what is desired is a field effect device that can be designed with increased length, increased maximum current, and improved SOA.